Publication Date

Summer 2010

Degree Type

Thesis

Degree Name

Master of Science (MS)

Department

Electrical Engineering

Advisor

David Parent

Keywords

Noise, Partition Noise, Reset Noise

Subject Areas

Engineering, Electronics and Electrical

Abstract

As Complementary Metal Oxide Semiconductor (CMOS) technology scales down,

partition noise may start to play a bigger role in reducing the signal-to-noise ratio (SNR)

in sample-and-hold circuits and other capacitive sensing circuits that reset the voltage

across a capacitor. Previous studies on partition noise lack a reliable and accurate

measurement method to quantify partition noise. In our study, we have developed a

method using Technology Computer Aided Design (TCAD) simulations to estimate

partition noise. Through simulation, we determined the transistor dimensions and sense

capacitance required to measure partition noise. Furthermore, we designed a test circuit

based on our simulation results with the flexibility to study partition noise. The test

circuit has a buffer that allows us to measure partition noise without interference from

test measurement equipments. Finally, we presented a method to measure and extract

partition noise using our test circuit.

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