Title

TCAD Framework for HCD Kinetics in Low VDDevices Spanning Full VG/VDSpace

Publication Date

11-1-2020

Document Type

Article

Department

Electrical Engineering

Publication Title

IEEE Transactions on Electron Devices

Volume

67

Issue

11

DOI

10.1109/TED.2020.3021360

First Page

4749

Last Page

4756

Abstract

The time kinetics of hot carrier degradation (HCD) is modeled using a reaction diffusion drift (RDD) framework. It is incorporated into Sentaurus Device TCAD and validated using conduction mode HCD data in n-and p-channel MOSFETs and FinFETs. RDD-enabled TCAD calculates carrier-energy-initiated generation of interface traps (Δ NIT) and the impact of the resulting localized charges on device parametric drift. HCD at various gate (VG) and drain (VD) biases spanning various modes (VG≤ and >VD) are simulated for low stress VD (< 3 V). The self-heating (SH)-effect-induced temperature (T) increase is invoked for FinFETs. Data from various experiments are analyzed and a wide range of power-law time kinetics slope (n) is explained.

Keywords

Hot carriers, interface trap generation, parametric drift, reaction diffusion drift (RDD) model, self-heating (SH) effect, technology CAD (TCAD)

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