Title

A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET

Publication Date

2-1-2020

Document Type

Conference Proceeding

Department

Electrical Engineering

Publication Title

2020 IEEE International Solid- State Circuits Conference - (ISSCC)

DOI

10.1109/ISSCC19947.2020.9063130

First Page

120

Last Page

122

Abstract

Internet of things (IoT) devices such as self-driven cars and home appliances are creating massive amounts of data traffic. Obviously, such demand trickles down to every electrical interface in a network. Therefore, next-generation data centers need to evolve accordingly to accommodate the bandwidth demand of a rapidly changing world of technology. Since the channel loss is not improving at the same rate, most of the standards are adopting multilevel signaling to make more efficient use of the frequency spectrum. A 4×112Gb/s PAM-4 transmitter presented in this work is leading this trend to keep electrical signaling viable and relevant for future data centers. It introduces three techniques to enable flexibility over different protocols and achieves 1.56pJ/b (175mW at 112Gb/s data rate including clocking) energy efficiency. First, improving signal-to-noise ratio is key to achieve lower BER in multilevel signaling. This work introduces a 'soft-switching' H-bridge output driver to enable a 1.2V peak-to-peak differential output swing without exposing devices beyond breakdown voltage. Second, 'flex clocking' is achieved by combining a central LC-PLL with a per-lane sub-sampling ring PLL. This combination enables flexible clock generation to seamlessly support data rates between 10Gb/s NRZ and 112Gb/s PAM-4. This clocking architecture enables low-frequency clock distribution for power saving and is easily scalable to more lanes. Third, a DSP-DAC-based transmitter is used to support an arbitrary number of equalization taps and different modulation schemes [1]. A segmented lookup-table-based (LUP-based) implementation further reduces the DSP power.

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