Effect of ReRAM Neuromorphic Circuit Array Variation and Fault on Inference Accuracy
Publication Date
1-1-2022
Document Type
Conference Proceeding
Publication Title
2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS)
DOI
10.1109/AICAS54282.2022.9869936
First Page
13
Last Page
16
Abstract
In this paper, we study the inference accuracy of Resistive Random Access Memory (ReRAM) based neuromorphic circuit under various array faults using fully analog SPICE simulations. The ReRAM Verilog-A model is calibrated to the experiment and a 45nm realistic Process Design Kit (PDK) is used. A handwritten dataset is used for the demonstration with a neural network containing 3 hidden layers. The faults studied include the random variations of ReRAM gap size due to gap size drifting and the 'stuck-off' faults with various spatial shapes in the ReRAM arrays. We also study how the faulty array location in the neural network affects circuit fault tolerance. Finally, we propose fault-aware processing and layout guidelines for extending the lifetime of ReRAM neuromorphic circuits for Internet-of-Things (IoT) applications.
Keywords
Fault, Inference Accuracy, Internet-of-Things (IoTs), Neuromorphic, ReRAM, SPICE simulation
Department
Electrical Engineering
Recommended Citation
Paul Quibuyen, Tom Jiao, and Hiu Yung Wong. "Effect of ReRAM Neuromorphic Circuit Array Variation and Fault on Inference Accuracy" 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS) (2022): 13-16. https://doi.org/10.1109/AICAS54282.2022.9869936
