Comparison of Manifold Learning Algorithms for Rapid Circuit Defect Extraction in SPICE-Augmented Machine Learning

Publication Date


Document Type

Conference Proceeding

Publication Title

2022 IEEE 19th Annual Workshop on Microelectronics and Electron Devices (WMED)




Identifying the source of integrated circuit (IC) degradation and being able to track its degradation via its electrical characteristics (e.g. the Voltage Transfer Characteristics, VTC, of an inverter) is very useful in failure analysis. This is because the electrical measurement is non-destructive, low-cost, and rapid. However, the extraction of defects from electrical characteristics requires significant domain expertise. To reduce or even obviate the need for domain expertise so that the process can be automatic for various circuits, one may use manifold learning. As a type of machine learning (ML), manifold learning also requires a large amount of accurate training data. To obtain enough defect training data, which is almost impossible from experiments, one may use SPICE simulation. Based on our previous work of using AutoEncoder (AE) to perform SPICE-augmented ML to extract the pMOS and nMOS source contact resistances from the inverter VTC, in this paper, we compare the efficacy of using another 6 types of manifold learning. They are used to predict the experimental result and it is found that most of them have reasonable performance although the AE is still the best (R2=0.9). However, when including also the variation of PMOS width (as a weak perturbation to the data), algorithms such as Locally Linear Embedding (LLE) are found to perform better than AE (R2=0.72) with LLE (R2=0.83) being the best. Therefore, multiple manifold learnings are suggested to be used in parallel in real production to enhance accuracy.

Funding Number


Funding Sponsor

National Science Foundation


Contact Resistant, Defects, Machine Learning, Manifold Learning, Reverse Engineering, SPICE Simulation


Electrical Engineering