Design of Bit Move Block using Bandwidth Arbitration for Master Slave Communication
Lecture Notes in Engineering and Computer Science
This paper illustrates the AMBA AXI4-Lite protocol bus model for multiple Master-Slave communication using bandwidth arbitration. A bit movement block is designed to perform read, modify, and write data into memory locations. Each bit move block consists of five configuration slave registers. The slave registers store source address, a destination address, and, a start bit. Bit move operation begins with start bit acknowledgment and the operation terminates with the done signal. Eight instances of this block act as masters, memory, and a total of 9 devices act as slaves. Master initiates the transfer by providing slave address, and slave acknowledges accordingly. Bandwidth allocation arbitrator is designed to select the master permitted to use the bus. An AXI-4 lite fabric is designed to establish connections between all these devices. The project aims to develop the best performing design which completes bit-move operation within a limited number of cycles. The project is designed in System Verilog.
AMBA AXI4-Lite, Arbitration, Bit movement, System verilog
Saranya Vasudevan and Lili He. "Design of Bit Move Block using Bandwidth Arbitration for Master Slave Communication" Lecture Notes in Engineering and Computer Science (2021): 140-145.