Publication Date


Document Type

Conference Proceeding

Publication Title

Lecture Notes in Engineering and Computer Science: Proceedings of The World Congress on Engineering 2022, 6-8 July, 2022, London, U.K



First Page


Last Page



The RISC-V processor's open-source architecture provides designers with flexibility in implementing the architecture for a variety of applications. The same advantage, however, makes the verification process difficult because all variations must be verified. The proposed project will create a verification environment for the extended RISC V architecture. RISC-V supports both the "M" standard extension for integer multiplication and division and the "Zicsr" standard extension for control and status register instructions. The above-mentioned ISA classes will be tested using the RV32I ISA-based DUT with a UVM environment around the DUT to verify the M and Zicsr functionalities. The M and Zicsr type ISA were verified with a 95% functional coverage. The UVM framework created can be re-used to verify other Instruction Set Architecture.


Instruction Set Architecture, M and Zicsr type ISA, RISC-V processor, RV32I based DUT, Universal Verification Methodology


This conference paper originally appeared in Proceedings of the World Congress on Engineering 2022, WCE 2022, July 6-8, 2022, London, U.K.. The paper can also be found online at:


Electrical Engineering