Design & Verification of AMBA AHB-Lite Memory Controller
2023 IEEE 13th Annual Computing and Communication Workshop and Conference, CCWC 2023
As technology advances, the on-chip communication bus architecture becomes increasingly prominent in interconnecting various components within the System-on-Chip (SoC). The standard ARM AMBA on-chip interconnect bus is designed as an SoC system's high-performance backbone bus, which supports faster communication with internal and external memories. This paper presented a memory controller design with an AMBA 3 AHB_lite standard based on a single master and multiple slave model. We verified the design as per the specifications of ARM using a System Verilog verification environment and functional coverage. Various testbench verification environment components such as transaction and generator (which generates the input stimulus), Driver (which drives input data to the Design Under Test (DUT)), Monitor (which monitors the signals from the DUT), and the Scoreboard (which reports about the design working condition) are developed to test single burst, wrapping, and increment bursts of various sizes (4, 8, and 16 beats) with waited transfer responses of the AHB_lite protocol. We also observed different corner cases during burst and wrap transfer.
AHB-Lite, AMBA 3, Memory Controller, SoC, System Verilog, verification, Verilog
Anila Kommineni, Manoj Kumar Gundu, Youngsoo Kim, and Shrikant Jadhav. "Design & Verification of AMBA AHB-Lite Memory Controller" 2023 IEEE 13th Annual Computing and Communication Workshop and Conference, CCWC 2023 (2023): 1307-1312. https://doi.org/10.1109/CCWC57344.2023.10099257