Publication Date
Spring 2010
Degree Type
Thesis
Degree Name
Master of Science (MS)
Department
Electrical Engineering
Advisor
David Parent
Keywords
cmos, delay, highspeed, model, optimization, propagation
Subject Areas
Engineering, Electronics and Electrical
Abstract
Propagation delay models, for CMOS Digital Circuits, provide an initial design solution for Integrated Circuits. Resources, both monetary and manpower, constrain the design process, leading to the need for a more accurate entry point further along in the design cycle. By verifying an existing propagation delay method, and its resulting delay model, calibration for any given process technology can be achieved. Literature reviews and detailed analysis of each step in the model development allow for greater understanding of each contributing parameter, and ultimately, adjustments to the model calibration result in a more accurate analytical model. An existing model was verified and improved upon using TSMC 0.18um and IBM 0.13um SPICE decks, and the resulting improvements can be used to further assist individuals needing a method and model for deriving an initial circuit design solution for integrated circuits.
Recommended Citation
Stamness, Rodger Lawrence, "Improvement of a Propagation Delay Model for CMOS Digital Logic Circuits" (2010). Master's Theses. 3790.
DOI: https://doi.org/10.31979/etd.4ch3-zc94
https://scholarworks.sjsu.edu/etd_theses/3790
