Publication Date
Spring 2014
Degree Type
Thesis
Degree Name
Master of Science (MS)
Department
Electrical Engineering
Advisor
Shahab Ardalan
Keywords
Cadence Virtuoso, Clock and Data Recovery (CDR), Delay Flip-Flop (DFF), Matlab and Simulink, Metastability, Phase-Locked Loop (PLL)
Subject Areas
Engineering
Abstract
Modeling delay flip-flops for binary (e.g., Alexander) phase detectors requires paying close attention to three important timing parameters: setup time, hold time, and clock edge-to-output (or briefly C2Q time). These parameters have a critical role in determining the status of the system on the circuit level. This study provided a guideline for designing an optimum DFF for an Alexander phase detector in a clock and data recovery circuit. Furthermore, it indicated DFF timing requirements for a high-speed phase detector in a clock and data recovery circuit. The CDR was also modeled by Verilog-A, and the results were compared with Simulink model achievements. Eventually designed in 45 nm CMOS technology, for 10 Gbps random sequence, the recovered clock contained 0.136 UI and 0.15 UI peak-to-peak jitter on the falling and rising edges respectively, and the lock time was 125 ns. The overall power dissipation was 21 mW from a 1 V supply voltage. Future work includes layout design and manufacturing of the proposed design.
Recommended Citation
Sargezisardrud, Alfred, "Delay Flip-Flop (DFF) Metastability Impact on Clock and Data Recovery (CDR) and Phase-Locked Loop (PLL) Circuits" (2014). Master's Theses. 4439.
DOI: https://doi.org/10.31979/etd.3xwa-ctg2
https://scholarworks.sjsu.edu/etd_theses/4439
