Master of Science (MS)
electrical overstress, failure mechanism, isothermal, Miller plateau, Power MOSFET, trap charge
This research focused on building a model based on collection of experimental data acquired with high electrical stressors at the gate of the power MOSFET under an isothermal condition to analyze certain deviations of intrinsic properties leading to degradation. The primary indicators were threshold shift, deviation in switching characteristics, and significant expansion of the Miller Plateau due to accelerated stressing of the device from the pristine condition. The intrinsic mechanism associated with the threshold shift and changes in the parasitic capacitances were observed and analyzed with mathematical precision and device parameter simulation. It was seen that, in addition to altered switching behavior and other changes, the threshold voltage shifted by 172%, the width of the Miller Plateau increased by 525%, and capacitances decreased by 24~43% at applied stress of 45V to 54V in addition to altered switching behavior and other changes. This behavior showed deviation; however, degradation did not occur. The root cause of the modified behavior of a stressed device was also analyzed. The 2D device-processing software "Sentaurus" correlated the experimental observations.
Mahiuddin, Shompa Shohiny, "Modeling of the impact of electrical stressors on the degradation process of Power MOSFETs" (2011). Master's Theses. 3943.