Master of Science (MS)
Bluetooth, Bluetooth low energy (BLE), CMOS, GPDK 45 nm, Low noise amplifier (LNA), RF front-end
With the increasing need for the Internet of things (IoT), Bluetooth low energy (BLE) technology has become a popular solution for wireless devices. The purpose of this thesis was to design a complementary metal-oxide-semiconductor (CMOS) low noise amplifier (LNA) for the Bluetooth low energy (BLE) front-end circuit. Forty-five nm CMOS technology was chosen for the design. The schematic was implemented in Cadence Virtuoso Schematic XL using the generic processing design kit (GPDK) 45 nm library and was simulated using Analog Design Environment (ADE). The LNA presented in this thesis achieved the lowest power consumption of 1.01 mW with a supply of 1 V. The LNA provided a reasonable gain which was 14.53 dB. Although the third-order input intercept point (IIP3) was low, which was -10.67 dBm, the noise figure (NF) achieved the lowest value, which was 0.98 dB at the center frequency of 2.44 GHz. This thesis emphasizes that CMOS RF front-end design, amplifier’s gain, linearity, and NF play critical roles in defining the circuit’s performance.
Hsiao, Chin-To, "Design of a 2.4 GHz CMOS LNA for Bluetooth Low Energy Application Using 45 nm Technology" (2017). Master's Theses. 4802.