Design Space of Vertical Ga2O3Junctionless FinFET and its Enhancement with Gradual Channel Doping
Publication Date
9-23-2020
Document Type
Conference Proceeding
Publication Title
2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia)
DOI
10.1109/WiPDAAsia49671.2020.9360255
Abstract
For the first time, we systematically study the design space of vertical Ga2O3 junctionless FinFET for 600V to 5kV ratings using TCAD simulation with experimentally calibrated parameters. Two scenarios are investigated, namely with "excellent"and "poor"gate oxide/channel interfaces. "Excellent"and "poor"interfaces result in no and severe surface mobility degradation, respectively. It is found that, for the "excellent"case, fin width (W) should be made as small as possible for optimal design. For the "poor"case, optimal W is ~200nm because ION degrades when W < 200nm. However, this can be alleviated by adopting a gradual channel doping scheme, which gives a ~30% boost in ION in the 600V application with a thinned wafer.
Funding Sponsor
San José State University
Keywords
Gallium Oxide, Junctionless, Power Device, TCAD, UWBG, Vertical FinFET
Department
Electrical Engineering
Recommended Citation
Adam Elwailly, Ming Xiao, Yuhao Zhang, and Hiu Yung Wong. "Design Space of Vertical Ga2O3Junctionless FinFET and its Enhancement with Gradual Channel Doping" 2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia) (2020). https://doi.org/10.1109/WiPDAAsia49671.2020.9360255
