TCAD Modeling of Cryogenic nMOSFET ON-State Current and Subthreshold Slope

Publication Date

9-27-2021

Document Type

Conference Proceeding

Publication Title

2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

DOI

10.1109/SISPAD54002.2021.9592586

First Page

255

Last Page

258

Abstract

In this paper, through careful calibration, we demonstrate the possibility of using a single set of models and parameters to model the ON current and Sub-threshold Slope (SS) of an nMOSFET at 300K and 5K using Technology Computer-Aided Design (TCAD). The device used is a 0.35 μm technology nMOSFET with W/L=10μm/10μm. We show that it is possible to model the abnormal SS by using interface acceptor traps with a density less than (2×10)12cm-2. We also propose trap distribution profiles in the energy space that can be used to reproduce other observed SS from 4K to 300K. Although this work does not prove or disprove any possible origin of the abnormal SS, it shows that one cannot completely rule out the interfacial traps as the origin and it shows that interfacial traps can be used to model the abnormal SS before the origin is fully understood. We also show that Drain-Induced-Barrier-Lowering (DIBL) is much reduced at cryogenic temperature due to the abnormal slope and the device optimization strategy might need to be revised.

Funding Number

2046220

Funding Sponsor

National Science Foundation

Keywords

Cryogenic CMOS, Sub-threshold Slope, Technology Computer-Aided Design

Department

Electrical Engineering

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