Study of Layout Dependent Radiation Hardness of FinFET SRAM using Full Domain 3D TCAD Simulation

Authors

Khoa Huynh, San Jose State University
Johan Saltin, San Jose State University
Jin Woo Han, NASA Ames Research Center
Meyya Meyyappan, NASA Ames Research Center
Hiu Yung Wong, San Jose State UniversityFollow

Publication Date

10-14-2019

Document Type

Conference Proceeding

Publication Title

2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

DOI

10.1109/S3S46989.2019.9320706

Abstract

Due to the emerging of novel technologies, such as stacked horizontal nanowires, and novel 3D integration schemes, such as stacking PMOS on top of NMOS, multiple transistors in a SRAM cell might be struck simultaneously by a single Alpha particle. This may result in worse radiation hardness of SRAM. We show that if the access transistor (A-NMOS) and pull-down transistor (PD-NMOS) are struck at the same time, bulk MOSFET SRAM (L_g,eff = 25nm) will be ∼20% more susceptible to Single Event Upset (SEU). Full domain 3D TCAD simulation of L_g=25nm FinFET SRAM cell is then performed to confirm that such scenario is possible even in a standard SRAM layout and the radiation hardness is reduced by as much as 50%. Therefore, DTCO of 3D integration should take radiation effect into account for critical mission applications.

Funding Number

N00164-19-1-1001

Funding Sponsor

U.S. Department of Defense

Keywords

3D TCAD Simulation, DTCO, FinFET, Layout, Radiation Hardness, SRAM

Department

Electrical Engineering

Recommended Citation

Khoa Huynh, Johan Saltin, Jin Woo Han, Meyya Meyyappan, and Hiu Yung Wong. "Study of Layout Dependent Radiation Hardness of FinFET SRAM using Full Domain 3D TCAD Simulation" 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (2019). https://doi.org/10.1109/S3S46989.2019.9320706