System Verilog versus UVM-based Verification of AXI4-Lite Arbitration
Publication Date
1-1-2023
Document Type
Conference Proceeding
Publication Title
Conference Proceedings - IEEE SOUTHEASTCON
Volume
2023-April
DOI
10.1109/SoutheastCon51012.2023.10115141
First Page
350
Last Page
357
Abstract
The communication bus is one of the critical components in System-of-Chip design. The on-chip bus communication architecture impacts the overall performance of an SoC design. As design complexity increases, they become more error-prone, and verification becomes challenging. According to a few studies, verification consumes about 70% of the total development time and is considered a bottleneck in the ASIC design cycle. This paper focuses on the design and verification of the AXI4-Lite arbitration algorithm. We present a design and implementation of a high-performance AXI4-Lite interconnect using System Verilog (SV) to connect three managers and six subordinate devices. We performed the verification of an AXI4-Lite arbitration system using two methodologies i.e., SV and Universal Verification Methodology (UVM). Several test cases were applied to check all possible scenarios for arbitration verification. The SV and UVM verification techniques are compared in this paper, and it is observed that the UVM methodology is a better choice for verifying large and complex designs.
Keywords
arbitration, AXI4-Lite, System Verilog (SV), Universal Verification Methodology (UVM), verification
Department
Electrical Engineering
Recommended Citation
Aiswariya Ramesh Babu, Pooja Anand, Youngsoo Kim, and Shrikant Jadhav. "System Verilog versus UVM-based Verification of AXI4-Lite Arbitration" Conference Proceedings - IEEE SOUTHEASTCON (2023): 350-357. https://doi.org/10.1109/SoutheastCon51012.2023.10115141
