Cryogenic Behaviors of 65nm Transistor: On-State IV and Parameters
Publication Date
1-1-2024
Document Type
Conference Proceeding
Publication Title
IEEE Workshop on Microelectronics and Electron Devices, WMED
DOI
10.1109/WMED61554.2024.10534143
Abstract
In this paper, the trend and variability of minimal size 65nm NMOS and PMOS transistors are measured and analyzed from 292K to 9.5K (for PMOS) and 4.2K (for NMOS). The changes and variability of the on-state current, threshold voltage, linear resistance, output resistance, and transconductance, which are important for analog applications, are extracted and analyzed. Empirical quadratic equations are developed to model the trend which can be used as handy tools for estimation. A simple methodology for rapidly calibrating the 4.2K BSIM model for the on-state currents of 65nm transistors is also proposed and demonstrated.
Funding Number
IO221107-03420-01
Funding Sponsor
Samsung
Keywords
Analog Circuit, BSIM, Compact Model, Cryogenic CMOS, Empirical Model, Variability
Department
Electrical Engineering
Recommended Citation
Po Shao Huang, Sahil Shah, Alhaji A. Sharka, Gilbert Kengni, Yuri Masuoka, and Hiu Yung Wong. "Cryogenic Behaviors of 65nm Transistor: On-State IV and Parameters" IEEE Workshop on Microelectronics and Electron Devices, WMED (2024). https://doi.org/10.1109/WMED61554.2024.10534143
