UVM-Based Design and Verification of AHB-Lite to AXI Bridge
Publication Date
1-1-2024
Document Type
Conference Proceeding
Publication Title
Conference Proceedings - IEEE SOUTHEASTCON
DOI
10.1109/SoutheastCon52093.2024.10500037
First Page
472
Last Page
479
Abstract
Over the last few decades, chip designing has evolved and become complex across several diverse areas, leading to increased verification time and effort. A longer verification process delays the completion of a design and sets back the time-to-market target. Universal Verification Methodology (UVM) provides flexible and reusable verification components that help us verify at the highest level and reduce verification time. Therefore, the proposed work is an implementation of an AHB-Lite to AXI bridge protocol and a UVM-based model that can fully verify the design. System-on-chip (SoC) designs widely use Advanced Microcontroller Bus Architecture (AMBA) standards for interconnections and implement a variety of buses to communicate with Intellectual Properties (IP). These designs can quickly become complex as more IPs are added to the SoC. Using Xilinx Vivado v2023.1, we successfully implemented a synthesizable bridge design and UVM testbench. We achieved 100% functional coverage and up to 98.75% code coverage.
Keywords
Advanced eXtensible Interface (AXI4), Advanced High-Performance Bus (AHB-Lite), Testbench, Universal Verification Methodology (UVM), Verification
Department
Electrical Engineering
Recommended Citation
Andres Bermudez Gamboa, Crispin Chipres, and Shrikant Jadhav. "UVM-Based Design and Verification of AHB-Lite to AXI Bridge" Conference Proceedings - IEEE SOUTHEASTCON (2024): 472-479. https://doi.org/10.1109/SoutheastCon52093.2024.10500037
