Design and Verification of an FPGA-Based MRI Image Cluster Processing
Publication Date
1-1-2025
Document Type
Conference Proceeding
Publication Title
Conference Proceedings IEEE SOUTHEASTCON
DOI
10.1109/SoutheastCon56624.2025.10971489
First Page
177
Last Page
186
Abstract
The FPGA-based MRI Cluster Image Processing System is designed to overcome the limitations of traditional MRI image processing, which often suffers from errors, high costs due to re-scans, and diagnostic delays. This system implements preprocessing techniques, such as median, average, and denoising filters, using a custom FPGA processor developed with System Verilog. In this work, we focused on enhancing image quality and processing speed. For example, the Peak Signal-to-Noise Ratio (PSNR) values for one of the cases are 36.21 dB and 36.03 dB, demonstrating competitive performance compared to Python and MATLAB. The FPGA method also achieves a Mean Squared Error (MSE) as low as 15.57 for one of the cases, highlighting reduced error rates. The results show that the FPGA system achieves superior throughput and reduced error rates, demonstrating its capability to deliver high-quality images in real-time with minimal distortion. Validated using the UVM methodology, the design ensures reliable parallel processing and scalability. This FPGA-based approach significantly improves over traditional MRI image processing methods, making it a more efficient and cost-effective solution for medical imaging applications.
Keywords
DMA, FPGA, Image Processing, MRI, System Verilog, UVM
Department
Electrical Engineering
Recommended Citation
Abhiram Reddy Duvvuru, Kumar Sai Reddy Guntaka, and Shrikant Jadhav. "Design and Verification of an FPGA-Based MRI Image Cluster Processing" Conference Proceedings IEEE SOUTHEASTCON (2025): 177-186. https://doi.org/10.1109/SoutheastCon56624.2025.10971489
