Publication Date

7-27-2026

Document Type

Article

Publication Title

IEEE Access

Volume

14

DOI

10.1109/ACCESS.2026.3717210

First Page

115142

Last Page

115153

Abstract

This paper presents a machine learning-based approach to correct inference errors caused by stuck-at faults in fully analog ReRAM-based neuromorphic circuits. Using a Design-Technology Co-Optimization (DTCO) simulation framework, the study models and analyzes six spatial defect types - circular, circular-complement, ring, row, column, and checkerboard - across multiple layers of a multi-array neuromorphic architecture for handwritten digit recognition tasks. It is demonstrated that the proposed correction method, which employs a lightweight neural network trained on the circuit's 10 output voltages, can improve inference accuracy from 55% to 90% (+ 35 percentage points) in highly degraded defective scenarios. Results show that even small corrective networks can significantly improve circuit robustness. This method offers a possible path toward enhanced yield and reliability for neuromorphic systems in edge and internet-of-things (IoTs) applications. In addition to correcting the specific defect types used during training, this method also demonstrates the ability to generalize, achieving reasonable accuracy when tested on different types of defects not seen during training.

Funding Number

2046220

Funding Sponsor

National Science Foundation

Keywords

Design-technology co-optimization (DTCO) framework, fault tolerance, inference accuracy, machine learning, neuromorphic computing, ReRAM, SPICE simulations, stuck-at faults

Creative Commons License

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.

Department

Electrical Engineering

Download

Share

COinS