DFT AI: Machine Learning-Guided Test Point Insertion for Pre-Silicon Debug and Post-Silicon Diagnosis in Complex VLSI Systems
Publication Date
1-1-2026
Document Type
Conference Proceeding
Publication Title
2026 IEEE 5th International Conference on AI in Cybersecurity Icaic 2026
DOI
10.1109/ICAIC67076.2026.11395827
Abstract
The rising complexity of modern System-on-Chip (SoC) designs has made it increasingly important to deploy intelligent Design-for-Testability (DFT) strategies that support both pre-silicon debug and post-silicon fault diagnosis. Conventional test point insertion (TPI) techniques are typically driven by static heuristics or ATPG-based analyses, and often struggle to scale in the presence of diverse microarchitectures, tight timing budgets, and strict area constraints. This paper introduces DFT AI, a machine learning-guided framework that automates TPI using data-driven reasoning and structural learning. The approach combines gradient-boosted decision trees with graph neural networks (GNNs) to estimate signal importance from structural, dynamic, and contextual features extracted from synthesized RTL designs. A constraint-aware selector ensures that only high-impact, timing-safe test points are chosen. We evaluate DFT AI on ITC'99 and OpenCores benchmark suites and observe up to 28% improvement in observability gain and a 27% reduction in diagnostic ambiguity over state-of-the-art methods, with modest area penalty and significantly reduced runtime. The framework generalizes well across heterogeneous designs and provides interpretability via SHAP-based signal analysis, offering a scalable and trustworthy solution for lifecycle-wide DFT automation.
Department
Interdisciplinary Engineering
Recommended Citation
Deepika Bhatia. "DFT AI: Machine Learning-Guided Test Point Insertion for Pre-Silicon Debug and Post-Silicon Diagnosis in Complex VLSI Systems" 2026 IEEE 5th International Conference on AI in Cybersecurity Icaic 2026 (2026). https://doi.org/10.1109/ICAIC67076.2026.11395827
