Publication Date
Spring 2013
Degree Type
Thesis
Degree Name
Master of Science (MS)
Department
Electrical Engineering
Advisor
Shahab Ardalan
Keywords
clock and data recovery, delta sigma, phase interpolator
Subject Areas
Electrical engineering
Abstract
This work focused on high-speed source-synchronous clock and multi-channel data receivers for inter-chip communications. Designs of inter-chip communication are becoming increasingly difficult with the rise in clock rates and the reduction in voltage supplies. Data transmissions at rates of gigabits per second require a fast and accurate clock and data recovery system on the front end of receivers.
Many designs allow for source-synchronous clocking architectures, but this work focused on a dual-loop with a phase-locked loop for frequency tracking and phase integrators for tracking each individual data lane. Limitations with the phase interpolator architecture cause systematic jitter, reducing the data eye.
Various techniques exist that aim to reduce or eliminate this systematic jitter from phase interpolator architectures. A technique based on digital lock detection was developed for this work that eliminates the phase interpolator systematic jitter.
Recommended Citation
Feng, Yu, "Novel Systematic Phase Noise Reduction Techniques for Phase Interpolator Clock and Data Recovery" (2013). Master's Theses. 4272.
DOI: https://doi.org/10.31979/etd.r5ax-2vqv
https://scholarworks.sjsu.edu/etd_theses/4272
