Publication Date
Summer 2014
Degree Type
Thesis
Degree Name
Master of Science (MS)
Department
Electrical Engineering
Advisor
Shahab Ardalan
Subject Areas
Engineering; Electrical engineering
Abstract
A Delay Flip Flop (DFF) is used in the phase detector circuit of the clock and data recovery circuit. A DFF consists of the three important timing parameters: setup time, hold time, and clock-to-output delay. These timing parameters play a vital role in designing a system at the transistor level. This thesis paper explains the impact of metastablity on the clock and data recovery (CDR) system and the importance of calibrating the DFF using a metastable circuit to improve a system's lock time and peak-to-peak jitter performance. The DFF was modeled in MATLAB Simulink software and calibrated by adjusting timing parameters. The CDR system was simulated in Simulink for three different cases: 1) equal setup and hold times, 2) setup time greater than the hold time, and 3) hold time greater than the setup time. The Simulink results were then compared with the Cadence simulation results, and it was observed that the calibration of DFF using a metastable circuit improved the CDR system's lock time and jitter tolerance performance. The overall power dissipation of the designed CDR system was 2.4 mW from a 1 volt supply voltage.
Recommended Citation
Waghela, Sagar, "Phase Locked Loop (PLL) based Clock and Data Recovery Circuits (CDR) using Calibrated Delay Flip Flop" (2014). Master's Theses. 4485.
DOI: https://doi.org/10.31979/etd.vn97-uetv
https://scholarworks.sjsu.edu/etd_theses/4485
