Publication Date
Fall 2016
Degree Type
Thesis
Degree Name
Master of Science (MS)
Department
Electrical Engineering
Advisor
Shahab Ardalan
Keywords
ADC, bio-implant, bio-medical, low-power, SAR
Subject Areas
Electrical engineering
Abstract
This thesis project involves the design and analysis of an 8-bit Successive Approximation Register (SAR) Analog to Digital Convertor (ADC), designed for low- power applications such as bio-medical implants. The sampling rate for this ADC is 500 KS/s. The power consumption for the whole SAR ADC system was measured to be 2.1 uW. The novelty of this project is the proposal of an extremely energy efficient comparator architecture. The result is the design of a final ADC with reasonable sampling speed, accuracy and low power consumption. In this project, all the different subsystems have been designed at the transistor level with 45 nm CMOS technology. The logical circuit was designed using Verilog language. It was then synthesized and integrated in the overall system.
Recommended Citation
Mazidi, Ehsan, "Design and Analysis of a Low-Power 8-Bit 500 KS/S SAR ADC for Bio-Medical Implant Devices" (2016). Master's Theses. 4767.
DOI: https://doi.org/10.31979/etd.tq8n-42kd
https://scholarworks.sjsu.edu/etd_theses/4767
