Publication Date
Summer 2017
Degree Type
Thesis
Degree Name
Master of Science (MS)
Department
Electrical Engineering
Advisor
Sotoudeh Hamedi-hagh
Keywords
Flash ADC, High-speed, Low-offset, Low-power, Offset cancellation, Time-based ADC
Subject Areas
Electrical engineering
Abstract
Low-power, medium resolution, high-speed analog-to-digital converters (ADCs) have always been important block which have abundant applications such as digital signal processors (DSP), imaging sensors, environmental and biomedical monitoring devices. This study presents a low power Flash ADC designed in nanometer complementary metal-oxide semiconductors (CMOS) technology. Time analysis on the output delay of the comparators helps to generate one more bit. The proposed technique reduced the power consumption and chip area substantially in comparison to the previous state-of-the-art work. The proposed ADC was developed in TSMC 65nm CMOS technology. The offset cancellation technique was embedded in the proposed comparator to decrement the static offset of the comparator. Moreover, one more bit was generated without using extra comparators. The proposed ADC achieved 4.1 bits ENOB at input Nyquist frequency. The simulated differential and integral non-linearity static tests were equal to +0.26/-0.17 and +0.22/-0.15, respectively. The ADC consumed 7.7 mW at 1 GHz sampling frequency, achieving 415 fJ/Convstep Figure of Merit (FoM).
Recommended Citation
Nasrollahpour, Mehdi, "Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology" (2017). Master's Theses. 4853.
DOI: https://doi.org/10.31979/etd.6wsv-p773
https://scholarworks.sjsu.edu/etd_theses/4853
