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Publication Date

Summer 2018

Degree Type

Thesis - Campus Access Only

Degree Name

Master of Science (MS)

Department

Electrical Engineering

Advisor

Youngsoo Kim

Keywords

Acceleration, ASIP, Compression, Convoluional Neural Networks, Inference

Subject Areas

Electrical engineering

Abstract

Convolutional neural networks (CNNs) require significant computing power during inference. Constrained devices, like smartphones or embedded systems, lack the resources required to run large neural network models at a usable speed without modifications to the model or specialized hardware. Methods for reducing memory size and increasing execution speed have been explored, but choosing effective techniques for an application requires extensive knowledge of the network architecture. This thesis proposes a general approach to preparing a compressed deep neural network for inference with minimal additions to existing microprocessor hardware. To show the benefits to this proposed approach, an example CNN for synthetic aperture radar target classification is modified and complimentary custom processor instructions are designed. The modified CNN is examined to show the effects of the modifications and the custom processor instructions are profiled to illustrate the potential performance increase from the new instructions. Up to 38x performance increase is achievable with 3% increase in gate count over the base Cadence LX7 processor with no classification performance degradation.

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