Publication Date
Fall 2018
Degree Type
Thesis
Degree Name
Master of Science (MS)
Department
Electrical Engineering
Advisor
Sotoudeh Hamedi-Hagh
Keywords
BGR, capacitor-less, IoT, LDO, load current
Subject Areas
Electrical engineering
Abstract
The motivation for this paper was to design a current feedback-based high load current, low drop-out (LDO) voltage regulator. A bandgap voltage reference (BGR) was also designed in conjunction with the LDO to simulate realistic environments. The schematic was designed with Cadence Virtuoso Schematic XL, using the Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS library, used for Internet of Things (IoT) System on Chip (SoC) applications. The proposed capacitor-less LDO with BGR provided an average temperature coefficient (TC) of 13.34 ppm/℃ within the range of -40 to 125 ℃. This was in accordance with military standards to gain a higher stability and power supply rejection ratio (PSRR). The proposed capacitor-less LDO also achieved a 200 mA load current with an error percentage of 0.246% and a -21.47 dB PSRR at 100 KHz with a current based structure. This thesis concluded with the application of capacitor-less LDO in medical IoT devices, followed by the future of medical device development.
Recommended Citation
Teoh, Melody, "Current Feedback-Based High Load Current Low Drop-Out Voltage Regulator in 65-nm CMOS Technology" (2018). Master's Theses. 4987.
DOI: https://doi.org/10.31979/etd.5366-23yt
https://scholarworks.sjsu.edu/etd_theses/4987
