Publication Date
Fall 2022
Degree Type
Thesis
Degree Name
Master of Science (MS)
Department
Computer Engineering
Advisor
Nima Karimian
Subject Areas
Computer engineering
Abstract
Many modern day applications can be solved with the usage of machine learning, which involves training a computer to learn on large amounts of data without direct programmer guidance. Conventional computers typically use normal general purpose central processing units, though more specialized tasks may take advantage of more parallel hardware such as graphics processing units. In the pursuit of increased performance to facilitate increasingly more complex machine learning models, researchers in both academia and industry look towards field-programmable gate arrays and application specific integrated circuits for their needs. Various implementations, both theoretical and practical, exist across a wide variety of designs. A custom design, using systolic arrays and built on the existing RISC-V Instruction Set Architecture, will be used to accelerate matrix calculations, with example performance on the MNIST dataset measured.
Recommended Citation
Wang, Miao, "A RISC-V Matrix Multiplier Using Systolic Arrays" (2022). Master's Theses. 5354.
DOI: https://doi.org/10.31979/etd.cm7w-2gse
https://scholarworks.sjsu.edu/etd_theses/5354
