TCAD-Spice Co-Simulation of Ferroelectric Capacitor as an Electrically Trimmable On-Chip Capacitor in Analog Circuit
Publication Date
10-14-2019
Document Type
Conference Proceeding
Publication Title
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
DOI
10.1109/S3S46989.2019.9320741
Abstract
In this paper, Ferroelectric Capacitor (FEC) is proposed as an electrically trimmable capacitor for integrated circuit applications and verified using TCAD-SPICE co-simulation. TCAD simulation is used to obtain the FEC capacitance by solving Landau-Khalatnikov (LK) Equation and Poisson Equation. TCAD mixed-mode simulation is used to study the stability of the circuit. FEC compact model is extracted and implemented in Verilog-A code. The FEC is then used in a single stage common source amplifier and, by changing the DC bias of the FEC from -5V to 0V, the 3dB bandwidth is shown to be trimmable electrically from 0.6GHz to 1.3GHz. The methodology also demonstrates the possibility of Design-Technology Co-Optimization (DTCO) of FEC in analog and RF circuits by using TCAD-SPICE co-simulation.
Funding Sponsor
San José State University
Keywords
capacitance trimming, DTCO, Ferroelectric capacitor, TCAD
Department
Electrical Engineering
Recommended Citation
K. Huynh, A. C. Tenkeu, K. P. Pun, and H. Y. Wong. "TCAD-Spice Co-Simulation of Ferroelectric Capacitor as an Electrically Trimmable On-Chip Capacitor in Analog Circuit" 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (2019). https://doi.org/10.1109/S3S46989.2019.9320741
