Enhancement-Mode Recessed Gate and Cascode Gate Junctionless Nanowire with Low-Leakage and High-Drive Current

Publication Date

9-1-2018

Document Type

Article

Publication Title

IEEE Transactions on Electron Devices

Volume

65

Issue

9

DOI

10.1109/TED.2018.2856740

First Page

4004

Last Page

4008

Abstract

Junctionless (JL) nanowire is a promising candidate for the future technology nodes because it obviates the need for ultrasteep junction formation. However, with high doping (e.g., 1x1020 cm-3) for large on-state current (ION) and low contact resistance, it becomes depletion mode (VTH <;0 V for nMOS and VTH > 0 V for pMOS). In order to have enhancement-mode device (VTH > 0 V for nMOS and VTH < 0$ V for pMOS), low doping (e.g., 1019 cm-3)is required, resulting in low current and high contact resistance. We propose two structures to alleviate the problem, which allow very high doping (e.g., 1.5 x1020 cm-3). The proposed concepts are validated by TCAD simulations using classical and quantum (nonequilibrium Green's function) transport models. The first one is to recess the nanowire under the gate region, resulting in enhancement-mode nMOS with >100% gain in ION. The second one is to have a cascode-/dual-gate structure which can further enhance ION , reduce IOFF and increase VTH with equivalent on-state gate length (LG = 5 nm and off-state LG = 10 nm and 50x increase in ION/IOFF ratio. Such ideas are applicable to other JL devices such as FinFET, SOI, and nanosheets.

Keywords

Enhancement mode, junctionless (JL), nanowire, nonequilibrium Green's function (NEGF), TCAD simulation

Department

Electrical Engineering

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