RTL to GDS Implementation and Verification of UART using UVM and OpenROAD
Publication Date
1-1-2024
Document Type
Conference Proceeding
Publication Title
2024 IEEE 14th Annual Computing and Communication Workshop and Conference, CCWC 2024
DOI
10.1109/CCWC60891.2024.10427771
First Page
713
Last Page
720
Abstract
The paper outlines a thorough Application Specific Integrated Circuit (ASIC) design flow for Universal Asynchronous Receiver and Transmitter (UART) utilizing RTL to GDS implementation and verification. Hardware verification employs the Universal Verification Methodology (UVM), while the OpenROAD tool is integrated for physical designs spanning synthesis to Graphic Data System (GDS). The paper states the relevance of UART in real-time systems, particularly in the context of the increasing prevalence of IoT and Big Data applications. It delves into the encountered challenges during the research project and offers recommendations for future advancements. Through our experimentations with the OpenROAD, we demonstrated the design and verification process of the sophisticated digital circuit. The results of the verification are shown via waveforms for test cases. The results of the backend implementation include layouts and a QoR (Quality of Results) report table. The paper concludes by stating the significance of each stage in the ASIC design cycle with future scope in optimizing the design for heightened frequencies and enhanced performance.
Keywords
ASIC, OpenROAD, Physical design, UART, UVM, Verilog
Department
Electrical Engineering
Recommended Citation
Purav Bhatt, Dharmik Joshi, and Shrikant Jadhav. "RTL to GDS Implementation and Verification of UART using UVM and OpenROAD" 2024 IEEE 14th Annual Computing and Communication Workshop and Conference, CCWC 2024 (2024): 713-720. https://doi.org/10.1109/CCWC60891.2024.10427771
