Comparative Analysis of Physical Design Parameters for JPEG Encoder IP using OpenROAD

Publication Date

1-1-2024

Document Type

Conference Proceeding

Publication Title

2024 IEEE 5th World AI IoT Congress, AIIoT 2024

DOI

10.1109/AIIoT61789.2024.10579002

First Page

533

Last Page

539

Abstract

A physical design engineer's goal is to optimize and scrutinize various timing and power-related parameters within a design. Understanding the behavior of these parameters is crucial for effective decision-making during the physical design flow. In this study, we conduct a comparative analysis using the OpenROAD framework to investigate the interactions between key input parameters (process node, and clock frequency,) and output parameters (slack, power, and voltage drop due to Internal Resistance) for a Joint Photographic Experts Group (JPEG) encoder IP. OpenROAD is used as the physical design flow for the backend implementation. It is an open-source framework for designing and implementing chips, just like Electronic Design Automation (EDA) toolchains. For a physical design engineer, estimating the trends is important as it helps while fixing the timing and Design Rule Check (DRC) violations. Through our experimentations with the OpenROAD tool, we observed the various expected trends between the input and output parameters of the flow. The results of the backend implementation include the layouts of various stages to validate the working of the flow. Finally, the trends are shown via 2D graphs. The interactions between the parameters offer a roadmap for selecting appropriate input parameters tailored to customer-specific requirements which ultimately enhances the overall efficiency and reliability of semiconductor products.

Keywords

floorplan, JPEG, OpenROAD, physical design, Process node, Slack, synthesis, timing

Department

Electrical Engineering

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